Alta Pattern Set			15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	
																			
CCD:	4710		#NAME?																
System:	16 Bit		- step 0 must be final resting  state																
Pattern	FEHS2																		
Date:	5/11/2012	Time (nS)	Data Latch				Clamp	Convert	INT 2	INT 1	RESET 2	RESET 1	SW	S3	S2	S1	R	Stop	Row
	Mask		0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	0	
	BIN 1	0	0	0	0	0	0	0	0	0	1	1	0	0	1	1	0	0	1
		10	0	0	0	0	0	0	0	0	1	1	0	0	1	0	0	0	2
		20	0	0	0	0	0	0	0	0	1	1	0	1	1	0	0	0	3
		30	0	0	0	0	0	0	0	0	1	1	0	1	0	0	0	0	4
		40	0	0	0	0	0	0	0	0	1	1	0	1	0	0	1	0	5
		50	0	0	0	0	1	0	0	0	1	1	0	1	0	0	1	0	6
		60	0	0	0	0	0	0	0	0	1	1	0	1	0	0	1	0	7
		70	0	0	0	0	0	0	0	0	1	1	0	1	0	0	0	0	8
		80	0	0	0	0	0	0	0	1	1	0	0	1	0	0	0	0	9
		90	0	0	0	0	0	0	0	1	1	0	0	1	0	0	0	0	10
		100	0	0	0	0	0	0	0	1	1	0	0	1	0	0	0	0	11
		110	0	0	0	0	0	0	0	1	1	0	0	1	0	0	0	0	12
		120	0	0	0	0	0	0	0	1	1	0	0	1	0	0	0	0	13
		130	0	0	0	0	0	0	0	1	1	0	0	1	0	0	0	0	14
		140	0	0	0	0	0	0	0	1	1	0	0	1	0	0	0	0	15
		150	0	0	0	0	0	0	0	0	1	0	0	1	0	0	0	0	16
		160	0	0	0	0	0	0	0	0	1	0	0	1	0	1	0	0	17
		170	0	0	0	0	0	0	0	0	1	0	0	0	0	1	0	0	18
		180	0	0	0	0	0	0	0	0	1	0	0	0	0	1	0	0	19
		190	0	0	0	0	0	0	0	0	1	0	0	0	0	1	0	0	20
		200	0	0	0	0	0	0	1	0	0	0	0	0	0	1	0	0	21
	 	210	0	0	0	0	0	0	1	0	0	0	0	0	0	1	0	0	22
		220	0	0	0	0	0	0	1	0	0	0	0	0	0	1	0	0	23
		230	0	0	0	0	0	0	1	0	0	0	0	0	0	1	0	0	24
		240	0	0	0	0	0	0	1	0	0	0	0	0	0	1	0	0	25
		250	0	0	0	0	0	0	1	0	0	0	0	0	0	1	0	0	26
	 	260	0	0	0	0	0	0	1	0	0	0	0	0	0	1	0	0	27
	 	270	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	28
		280	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	29
		290	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	30
	 	300	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1	31
	END	310	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	32